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JTAG Technology - Seminar & Workshop

Post time:  2009-11-26 07:17
 

Author:1258092593329

Points:  135

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http://events.linkedin.com/JTAG-Technology/pub/165362
 
One-Day Course on Using JTAG Technology for Software Debugging
Date: Thursday, December 17, 2009
Place: Hotel The Capitol, Raj Bhavan Road, Bangalore -560 001. Tel: 91 80 2228 1234
Time: 9.30 AM to 5.00 PM.

COURSE CONTENTS
1. Conventional Methods of Software Debugging
a) Debug Monitor.b) In -Circuit Emulator.
c) Debug Messages and Indicators.
d) Scope and Limitations of these methods.

2. JTAG Technology – An Introduction
a) The Boundary Scan Architecture.
b) Test Access Port (TAP).
c) Access to System Bus, Memory, Instructions and Data.
d) Scope and Limitations for Debug.

3. JTAG Requirements for Basic Debugging Features
a) Introduction to Debug Architecture of Microprocessor – ARM7 as an example.
b) JTAG access to processor internals through processor’s Debug Architecture.
c) Breakpoints–Software, Hardware and Complex.

4. Debugging for Board Bring Up.
a) Register files and processor initializations.
b) Libraries for debugging support.

5. Flashing from a debugger using JTAG access
a) Flash utilities.
b) Programming Flash though boundary Scan.

6. JTAG Requirements for Advanced
Debugging Features
a) Real-time or full speed debugging.
b) Trace, Trace Buffers and Triggers.
c) Support for Trace through JTAG.

7. Insights into JTAG adapters
a) Types, how and where debug code executes.
b) Connector and connectivity.
c) Emulation Memory.

In addition to lectures, the above topics, where required, will be demonstrated using appropriate tools
– JTAG Emulators, and Software Debuggers.
Prerequisite: Knowledge in C Programming, any Assembly Language and Micro Processor and or Micro
Controller Architecture is mandatory to attend this course.

Speaker's Profile:
P Seshan has about 25 years of industry experience. This includes extensive programming experience in Assembly,
C, Pascal, FORTRAN, Modula 2, and Hardware board design and implementation, Project Management, and
Multi functional engineering. He has expertise in Board bring up, Device Drivers and Emulators. He holds B.E
(Hons) in Electrical and Electronics Engineering from Birla Institute of Technology and Sciences (BITS), Pilani,
India, and PGDIM in General Management.

Course Fees: Rs. 1500.00 (One Thousand Five Hundred Rupees per attendee).
Course Fee includes
Presentation Materials, Lunch, Tea and Coffee.
For Registration please contact jtag@esds.in or 080-4214 6835
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Reply:  JTAG Technology - Seminar & Workshop Post time:  2009-11-25
 

Author:1258092593329

Points:  135

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